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Physical Design Engineer (Onsite)

Bay Area, CA

Job Description:

Location – Bay Area, CA (Onsite)


 

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·        Hands-on experience with FinFET technologies is an advantage


Moiz

Email: moiz@ecomputertech.com

P: 972 996 2024 & 972-889-1818 x 106


Key Skills:

  • placement guidelines, clock-tree synthesis, routing, timing optimizations, (DRC/LVS/DFM, chip finishing)

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Job Information

  • Date Posted
    09-08-2023
  • Location
    Bay Area, CA
  • Job Type
    Contract

Job Skills

placement guidelines, clock-tree synthesis, routing, timing optimizations, (DRC/LVS/DFM, chip finishing)